The present invention relates to programmable logic devices, and more particularly to methods for testing and using programmable logic devices that contain minor defects.
Programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs), are user-programmable integrated circuits that can be programmed to implement user-defined logic circuits. In a typical architecture, an FPGA includes an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs). A hierarchy of programmable routing resources interconnects the CLBs and IOBs. Loading a configuration bitstream into configuration memory cells of the FPGA customizes these CLBs, IOBs, and programmable routing resources. Additional resources, such as multipliers, memory, and application-specific circuits may also be included.
PLDs are growing ever larger as vendors attempt to satisfy customer demand for PLDs capable of performing ever more complex tasks. Unfortunately, as chip size increases, so too does the probability of finding a defect on a given chip. The process yield therefore decreases with PLD complexity, making already expensive PLDs still more expensive.
PLDS are not design specific, but instead afford users (e.g., circuit designers) the ability to instantiate an almost unlimited number of circuit variations. Not knowing in advance the purpose to which a given PLD will be dedicated places a heavy burden on the quality and reliability of the PLD because PLD vendors must verify the functionality of any feature that might be used. To avoid disappointing customers, PLD manufacturers discard PLDs that include even relatively minor defects.
PLD defects can be categorized in two general areas: gross defects that render the entire PLD useless or unreliable, and localized defects that damage a relatively small percentage of the PLD. It has been found that, for some large chips, close to two thirds of the chips on a given wafer may be discarded because of localized defects. Considering the costs associated with manufacturing large integrated circuits, discarding a large percentage of PLD chips has very significant adverse economic impact on PLD manufacturers.
The present invention enables PLD manufactures to identify PLDs that, despite some defects, can flawlessly implement selected customer designs.
Subsequent to fabrication, the various chips on a given semiconductor wafer are tested for xe2x80x9cgrossxe2x80x9d defects, such as power-supply shorts, that have a high probability of rendering a PLD unfit for any customer purpose. In a test methodology applicable to SRAM-based FGPAs, chips that survive gross testing are subjected to a xe2x80x9creadback testxe2x80x9d to verify the function of the configuration memory cells. Defect-free chips are subjected to further testing to ensure flawless performance, while chips that exhibit a large number or dense concentration of readback defects are rejected. Chips with relatively few defects are set-aside. as xe2x80x9cASIC candidatesxe2x80x9d and are subjected to further testing. Unlike the general tests normally performed to verify PLD functionality, in one embodiment the ASIC candidates are subjected to application-specific tests that verify the suitability of each candidate to function with one or more specific customer designs.
Some test methods in accordance with embodiments of the invention employ test circuitry derived from a user design to verify PLD resources required for the design. These methods verify the suitability of an FPGA for a given design without requiring an understanding of the design, and therefore greatly reduce the expense and complexity of developing design-specific tests for a user design. Also advantageous, narrowing test scope to those resources required for a given design reduces the time required for testing and increases the number of saleable PLDs. Using test circuits other than the user design to test the resources required for the user design facilitates comprehensive testing without requiring an understanding of the user design.
The foregoing test methods will not forestall PLD vendors from selling fully tested, defect-free PLDs. Customers will still require defect-free PLDs to develop customer-specific designs and to bring these designs to market quickly. However, once a customer has a specific design, the aforementioned test procedures can provide reduced-cost PLDs that are physically and functionally identical to the fully functional PLD or PLDs first used to develop the customer-specific design.
In accordance with one embodiment of the invention, a customer interested in the potential cost savings associated with recovered PLDs will send an expression of the customer-specific design (e.g., a data file) to the PLD vendor. The vendor will then use the expression to test ASIC candidates in the manner described above. ASIC candidates that are physically and functionally identical to the defect-free PLD first used to instantiate the customer-specific design can then be sold to the customer at reduced cost.
This summary does not limit the scope of the invention, as the scope of the invention is defined by the claims.